Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. As used herein, “include” and “including” mean including without limitation.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (“programming”) sequence.
For all of these programmable logic devices (“PLDs”), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, e.g., using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.
Generally, with respect to dataflow networks, an “actor” may be described as a processing element that consumes and produces data. The consumption and the production of data is generally considered to be in a form known as a “token.” When constructing an implementation of a dataflow network from a dataflow specification with regard to sizing of queues between actors, such queues may have a depth which is excessive. For example, if queues are implemented with first-in, first-out buffers (“FIFOs”), then such FIFOs may have the ability to hold more tokens than may be processed at a time when operating such a dataflow network. Having FIFOs that are too large consumes resources unnecessarily, which may unnecessarily increase the cost of an implementation of such a dataflow specification. Contrastingly, if such FIFOs are made too small, the resulting dataflow network may be slowed unnecessarily. Moreover, if such FIFOs in a dataflow network are too small, a deadlock condition may result.
If a dataflow network may be scheduled statically, such as a Synchronous Dataflow (“SDF”) network or a Cyclo-Static Dataflow (“CSDF”) network, it may be possible to analytically determine queue sizes for a variety of targeted performance parameters. These targeted performance parameters may preclude such a dataflow network from deadlocking.
However, in a dataflow network where data consumption and data production of actors are data dependent, it is not possible to analytically determine queue sizes to avoid deadlock of such a dataflow network. Thus, a designer has to determine appropriate queue sizes based on prior experience or particular knowledge of the application. However, even though it may have been possible for a designer to include queue sizes that precluded deadlocks, such queue sizes may have still been too large, leading to unnecessary consumption of queue resources.